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In this article, I will guide you through the basics of conducting an EMI project review for a Printed Circuit Board layout.
The focus will be on a motherboard design featuring AllWinner-A64 processors, a relatively complex system.
The project we are going to review is the TERES-I from Olimex.
As EMI specialists, we’ll explore the critical areas to address in order to optimize the board’s EMI performance.
PCB Stackup
One of the first things I check during an EMI review is whether the stackup is correct.
Getting the stackup right accounts for about 90% of the EMI performance.
Why is that?
Because the stackup determines how the electromagnetic fields are contained within the PCB.
What do I mean by that?
In PCB design, layers always come in pairs.
For example, if I have a signal layer, there must automatically be a return reference plane (RRP) adjacent to it—this should be second nature.
What does "adjacent" mean?
It means the return reference plane should be directly above or below the signal layer.
It’s important that the return reference plane (RRP) is placed as close as possible to the signal layer to do its job effectively.
As the name suggests, the RRP provides the return path for the current to flow back to its source, and it also offers a reference potential for the signal layer.
If this setup is not in place, we are likely to face EMI issues as well as signal integrity problems. This is because, without proper containment, the electromagnetic fields can "spread out" rather than being confined by the stackup.
When the RRP is placed as close as possible to the signal layer, the electromagnetic fields remain "smaller" and more controlled.
One key point to highlight is that the power layer does not work well as a return reference plane.
This is because, for the return current to flow back to its source, it would need to cross multiple layers before finally closing the loop and reaching the source pin. This leads to poor EMI performance and signal integrity.
What does this mean?
It means that the return current must travel through the space between the layers, which has its own impedance. As the current flows through this space, it creates a voltage drop that introduces noise within the stackup.
This noise can lead to crosstalk between signals on adjacent layers and may even cause emissions from the edges of the board.
For this reason, I do not recommend using the power plane as a return path, especially for high-speed signals.
You might have heard suggestions about using stitching capacitors, but the issue is that the impedance of these capacitors at high frequencies tends to be inductive.
This means that the high-frequency portion of the return current will not flow through the decoupling capacitor; instead, it will travel through the layers as displacement current.
As a result, this displacement current will spread between the layers, seeking the path of least impedance to return to the source and complete the current loop.
In contrast, the low-frequency portion of the current flowing through the decoupling capacitor often takes a larger loop, which can create common mode currents that lead to emissions.
For these reasons, we should avoid using the power layer as a return layer.
At least, I no longer do!
Optimal 6 Layers Stackup
We can immediately see that the stackup is composed of 6 layers.
I expect to see at least two Return Reference Planes (RRP) because each signal should have an RRP adjacent to it, or at least on one side where it couples.