How can this create EMI issues?
One of the things I am starting to notice more often during EMI PCB Design Reviews is that the importance of reducing the inductance of the return and reference path is often overlooked.
What I’m seeing is that the pads requiring the lowest inductance connection, in this case, the GND pads, are being left for routing in the final stages instead of at the beginning.
One of the first phases of layout design should be placing the vias that connect to the Return and Reference Plane (RRP).
However, I often observe that these nets are left to be connected at the end of the design process, resulting in insufficient low-inductance connections, and not enough space to route them appropriately.
For example, this happens when two pads share the same vias or when pads are connected to polygon fills that are not properly connected to the RRP with low inductance as they should be.
Connecting these nets to polygon fills doesn’t guarantee a low-inductance connection to the RRP.
From an EMI perspective, this can lead to differences in voltage potential in the return path.
These voltage sources in the return path are among the biggest contributors to conducted emission issues.
So, if you want to avoid failing an EMC test, I highly encourage you to prioritize the connections of these return and reference nets at the start of the design phase, not at the end.
Hope this helps!
Dario
fresuelectronics.com
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